Merenda et al. synthesize an applied, hardware-to-software pipeline for edge ML and give a concrete, reproducible-seeming worked example; their novelty lies in bringing together algorithmic compression, hardware selection, offloading strategies, and privacy approaches in a single practical review aimed at practitioners deploying ML on microcontrollers and edge accelerators
The paper's MNIST example includes concrete toolchain steps and per-layer timing and memory tables (Tables 5β7), enabling reasonably direct reproduction on the same ST hardware and toolchain (X-CUBE-AI + NUCLEO-F746ZG + TensorFlow/Keras). However, full reproducibility would require sharing of model files, pruning/quantization scripts and exact X-CUBE-AI settings β these are not published within the article (data availability: not specified) so reproducibility is moderate but incomplete
Authors declare no conflict of interest and report no external funding; acknowledgments list a regional program. This reduces risk of obvious sponsor bias but does not preclude implicit platform/vendor emphasis (several ST tools and STM boards are used in the worked example) β practitioners should note that the MNIST pipeline is ST-centric and adapt to other vendors accordingly
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